Hardware-Enabled Sovereignty: Securing Military Systems Through a Novel and Resilient Defense Architecture
In: 2026 18th International Conference on Cyber Conflict (CyCon)
doi.org/10.23919/CyCon70911.2026.11609427
The increasing complexity of cyberattacks on military systems, coupled with their extended life- times (often ten to twenty years), poses a critical threat to operational integrity and availability. Traditional cyberdefense measures like endpoint detection and response (EDR) and intrusion detection systems (IDSs) are often not feasible in these systems as they require cloud integration, may compromise the required level of information classification, expand the attack surface, and potentially impair the military systemâs sovereignty. Attackers may also pursue dual objectives: an immediate, high-impact assault that destroys mission capabilities, or a complex, stealthy campaign to exfiltrate data or embed persistent footholds for fu- ture operations. This paper leverages the Sovereign architecture to mitigate these challenges. The Sovereign Project researches the architecture of a holistic cyber defense platform for enhancing the cybersecurity of critical infrastructures (CIs) using a sovereign, modular, resilient, hardware-based, AI-driven and zero- trust-based approach. The modular design enables independent integration of its components into existing systems to address special operational requirements. Sovereign deploys a novel network sensor architec- ture â sovereign sensor and actuator (SOSA) â utilizing a hardware design based on field programmable gate arrays (FPGAs) and an application specific processor (ASP) system on chip (SoC) as its core. This core significantly reduces the attack surface, hardens the system, and increases its resilience against a wide range of attacks. This paper focuses on the SOSA and its adaptations to operate in a military environment. It analyzes the standalone deployment advantages, protection capabilities, and the sensorâs support against the duality of objectives. A practical adaptation to SOSA for a naval combat management system (CMS), validates the presented approach through a working implementation. The principles and techniques of using ASPs to harden and improve system resilience are applicable to a wide range of military areas, which the paper briefly highlights.
Trustworthiness by Structural Elimination
In: 29th Forum on Specification and Design Languages
Typically, developers achieve hardware trustworthiness by adding security modules, redundancy, or verification engines, increasing area requirements, energy consumption, and complexity. We propose trustworthiness by structural elimination, generating hardware directly from application code so that only required functionality exists physically. Our methodology eliminates unused code paths to produce a minimal, correct architecture, achieving correctness, reliability, security, and energy efficiency simultaneously without additive components.
SOVEREIGN - Towards a Holistic Approach to Critical Infrastructure Protection
In: Proceedings of the 19th International Conference on Availability, Reliability and Security
doi.org/10.1145/3664476.3671410
In the digital age, cyber-threats are a growing concern for individuals, businesses, and governments alike. These threats can range from data breaches and identity theft to large-scale attacks on critical infrastructure. The consequences of such attacks can be severe, leading to financial losses, threats to national security, and the loss of lives. This paper presents a holistic approach to increase the security of critical infrastructures. For that, we propose an open, self-configurable, and AI-based automated cyber-defense platform that runs on specifically hardened devices and own hardware, can be deeply embedded in critical infrastructures and provides full visibility on network, endpoints, and software. In this paper, starting from a thorough analysis of related work, we describe the vision of our SOVEREIGN platform in the form of an architecture, discuss individual building blocks, and evaluate it qualitatively with respect to our requirements.
A Modern Approach to Application Specific Processors for Improving the Security of Embedded Devices
In: IECON 2021-47rd Annual Conference of the IEEE Industrial Electronics Society
doi.org/10.1109/iecon48115.2021.9589730
The security of embedded devices is very important today because critical infrastructures like medical devices, transportation, communication, and smart grids deploy them in large numbers. In all of these areas cybersecurity is the enabler for safety as failing or compromised devices threaten the life of people. Often, it is not feasible securing already deployed devices because of high costs, missing physical access, or defective hardware. Therefore, the next generation devices deployed in the future have to be more secure and more resilient to cyber attacks. This paper proposes a new approach to secure these next generation devices by using program optimized Application Specific Processors (ASPs) and employing an easy to integrate development flow for embedded developers. It evaluates the security improvement by analyzing the vulnerability of the approach against typical attack patterns.
HDL FSM Code Generation Using a MIPS-based Assembler
In: 2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)
doi.org/10.1109/isie.2019.8781095
The implementation of Finite State Machines (FSMs) is a recurring task in the development of embedded systems when Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) are being designed. The standard implementation language for these FSMs in this context is a Hardware Description Language (HDL) like VHDL or Verilog. The implementation complexity can rise quickly depending on FSM size and which devices/components are controlled. In many cases FSMs enforce sequential execution of instructions in the concurrent world of FPGAs or ASICs. This paper proposes the use of a MIPS-based assembly dialect and assembler called aFSM to decrease the implementation complexity of such FSMs by automatically generating the FSMs VHDL code. A human VHDL implementation of an Ethernet controller with an FPGA is compared against the implementation with aFSM to evaluate the assembler.